1. Field of the Invention
The present invention relates to a function clock (gated clock) signal generation circuit of, for example, a synchronous D-type flip-flop equipped with an enable function useful for reduction of the area of a E large-scale integrated circuit (LSI) of a complementary metal oxide semiconductor (CMOS) and reduction of the power consumption and to a D-type flip-flop equipped with an enable function and a memory circuit using the same.
2. Description of the Related Art
The increasingly larger size and complexity of LSIs means that a single type of clock is no longer sufficient. There is therefore a growing need for use of a plurality of clocks in a single chip.
The reason why a plurality of clocks are used is that, in general, the contents of the processing of different blocks are different. In recent large-scale high performance LSIs, however, in addition to this, the increase of the power consumption has become a serious problem. As one of the measures taken against this, useless operations are being reduced by using a large number of function clocks optimum for the processing of the blocks.
Below, an explanation will be made of a case where use is made not a plurality of clocks having a completely asynchronous relationship, but a plurality of clocks which are prepared by frequency division of an original clock and by clock pulse selection and which are synchronized with the original clock.
As examples of the related art where such a plurality of clocks are necessary, there is the system for generation of a function clock by a gate, a system using a D-type flip-flop equipped with an enable function which makes an equivalent operation to that of the case using a plurality of clocks be performed by using a single single-phase clock and a D-type flip-flop equipped with an enable function, and a system for generation of a function clock which samples an enable signal once by a D-type flip-flop and then generates a function clock by using a gate.
With these related arts, however, as will be explained in detail later with reference to the drawings, there are the problems of a large interconnection area and cell area, a large power consumption, and difficult design of timing in the function clock generation circuit and in the D-type flip-flop equipped with an enable function and the memory circuit using the same.